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| `define ADD 3'd0
`define ADDI 3'd1
`define NAND 3'd2
`define LUI 3'd3
`define SW 3'd4
`define LW 3'd5
`define BNE 3'd6
`define JALR 3'd7
`define EXTEND 3'd7
`define IOP 15:13 // opcode
`define IRA 12:10 // rA
`define IRB 9:7 // rB
`define IRC 2:0 // rC
`define IIM 6:0 // immediate (7-bit, to be sign-extended)
`define ILI 9:0 // large unsigned immediate (10-bit, to be 0-extended)
`define ISB 6 // immediate's sign bit
`define ZERO 16'd0
`define HALTINSTRUCTION { `EXTEND, 3'd0, 3'd0, 3'd7, 4'd1 }
module RiSC (clk);
input clk;
reg [15:0] rf[0:7];
reg [15:0] pc;
reg [15:0] m[0:65535];
reg [15:0] m1;
reg [2:0] iop,ira,irb,irc;
reg [6:0] iim;
reg [9:0] ili;
wire isb;
reg [15:0] imm, imma;
always @(negedge clk) begin
rf[0] <= `ZERO;
end
assign isb = m[pc[6]];
always @(posedge clk) begin
m1 = m[pc];
iop = m[pc[15:13]];
ira = m[pc[12:10]];
irb = m[pc[9:7]];
irc = m[pc[2:0]];
iim = m[pc[6:0]];
ili = m[pc[9:0]];
imm = {ili,5'b0};
if( iop == ADD) begin
rf[ira] <= rf[irb] + rf [irc];
pc <= pc + 1;
end
else if (iop == ADDI) begin
if(!isb) begin
rf[ira] <= rf[irb] + iim;
pc <= pc+1;
end
else if(isb) begin
rf[ira] <= rf[irb] - iim;
pc <= pc+1;
end
end
else if (iop == NAND) begin
rf[ira] <= ~(rf[irb] && rf[irc]);
pc <= pc+1;
end
else if (iop == LUI) begin
imm = {ili,5'b0};
rf[ira] <= imm;
pc <= pc + 1;
end
else if (iop == SW) begin
if (!isb) begin
imma <= iim + rf[irb];
m[imma] <= rf[ira];
pc <= pc+1;
end
else if (isb) begin
imma <= rf[irb] - {10'b0,iim[5:0]};
m[imma] <= rf[ira];
pc <= pc+1;
end
end
else if (iop == LW) begin
if (!isb) begin
imma <= iim + rf[irb];
rf[ira] <= m[imma] ;
pc <= pc+1;
end
else if (isb) begin
imma <= rf[irb] - {10'b0,iim[5:0]};
rf[ira] <= m[imma] ;
pc <= pc+1;
end
end
else if (iop == BNE) begin
if (rf[ira] != rf[irb])
begin
if (!isb)
pc <= pc + 1 + iim;
else if (isb)
pc <= pc + 1 + {10'b0,iim[5:0]};
end
else
pc <= pc+1;
end
else if (iop == JALR) begin
pc <= rf [irb];
ira <= pc + 1;
end
else if (iop == `HALTINSTRUCTION) begin
pc <= 0;
$stop;
end
end
endmodule |