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Simple Processor VHDL Doubt

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apoorvmintri

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Hey Guys,

Just joined this forum. I had some doubts regarding initializing RAM with my processor I designed in VHDL, I am still a noob with VHDL. It's 16-bit simple processor (VHDL) for a Cyclone II FPGA - Altera DE2 Board.

I submitted this on another forum, but haven't received any reply. So re-posted here, seems that people here are more helpful.

I have a 128 words and each word being 16 bit of course memory. I have tried several ways of instantiating this MIF file, but my registers don't seem to do anything. Before trying to add RAM, I had absolutely no issues. The functional simulation was perfect, but now....:-?

At present, before making it more complex I decided to keep it simple with it's instructions:

Operation Function performed
ld Rx,[Ry] Rx ← [[Ry]]
st Rx,[Ry] [Ry] ← [Rx]
mvnz Rx, Ry if G != 0, Rx ← [Ry]
AND add & sub

So the VHDL coding basically allows the processor to read the state of some switches on the board. The switch values should be stored into a register, and the processor should be able to read this register by using a ld instruction.

Below is the component for memory:
COMPONENT proc
PORT ( DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Resetn, Clock, Run : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
W : OUT STD_LOGIC;
Done : BUFFER STD_LOGIC);
END COMPONENT;

It's port mapped-
inst_mem_cs <= '1' WHEN ADDR(15 DOWNTO 12) = "0000" ELSE '0';
-- inst_mem (address, clock, data, wren, q);
U4: inst_mem PORT MAP (ADDR(6 DOWNTO 0), Clock, DOUT, inst_mem_cs AND W,
inst_mem_q);

ADDR is from the Data

Below is the MIF file explaining the different cases for loading/moving register values:

% This code scrolls back and forth the letters dE2 across the 7-segment displays
% and also displays a count (in register R2) on the red LEDs. The speed of scrolling,
% and counting, is controlled by the 16-bit value read from switches SW15-0.
00 : 0010000000000000; % mvi R0,#1 K
01 : 0000000000000001;
02 : 0000010000000000; % mv R1,R0 1
03 : 0011100000000000; % mvi R6,#Beta Q <- *'D'
04 : 0000000001100110;
05 : 0010100000000000; % mvi R2,#0 [LED]
06 : 0000000000000000;
07 : 0001011100000000; % Loop mv R5,R6 P <- Q
08 : 0011000000000000; % mvi R4,#H7_address
09 : 0010000000000000;
0A : 1000111010000000; % ld R3,R5 [P]
0B : 1010111000000000; % st R3,R4 H7 <- [P]
0C : 0101010010000000; % add R5,R1 P++
0D : 0101000010000000; % add R4,R1 H6
0E : 1000111010000000; % ld R3,R5 [P]
0F : 1010111000000000; % st R3,R4 H6 <- [P]
10 : 0101010010000000; % add R5,R1 P++
11 : 0101000010000000; % add R4,R1 H5
12 : 1000111010000000; % ld R3,R5 [P]
13 : 1010111000000000; % st R3,R4 H5 <- [P]
14 : 0101010010000000; % add R5,R1 P++
15 : 0101000010000000; % add R4,R1 H4
16 : 1000111010000000; % ld R3,R5 [P]
17 : 1010111000000000; % st R3,R4 H4 <- [P]
18 : 0101010010000000; % add R5,R1 P++
19 : 0101000010000000; % add R4,R1 H3
1A : 1000111010000000; % ld R3,R5 [P]
1B : 1010111000000000; % st R3,R4 H3 <- [P]
1C : 0101010010000000; % add R5,R1 P++
1D : 0101000010000000; % add R4,R1 H2
1E : 1000111010000000; % ld R3,R5 [P]
1F : 1010111000000000; % st R3,R4 H2 <- [P]
20 : 0101010010000000; % add R5,R1 P++
21 : 0101000010000000; % add R4,R1 H1
22 : 1000111010000000; % ld R3,R5 [P]
23 : 1010111000000000; % st R3,R4 H1 <- [P]
24 : 0101010010000000; % add R5,R1 P++
25 : 0101000010000000; % add R4,R1 H0
26 : 1000111010000000; % ld R3,R5 [P]
27 : 1010111000000000; % st R3,R4 H0 <- [P]
28 : 0111100000000000; % sub R6,R0 Q <- Q - K
29 : 0011010000000000; % mvi R5,#Alpha-1
2A : 0000000001100000;
2B : 0011000000000000; % mvi R4,#Skip
2C : 0000000000110110;
2D : 0111011100000000; % sub R5,R6 Q == Alpha-1?
2E : 1101111000000000; % mvnz R7,R4 No
2F : 0101100010000000; % add R6,R1
30 : 0101100010000000; % add R6,R1 Q <- Alpha+1
31 : 0011010000000000; % mvi R5,#1111111111111111
32 : 1111111111111111;
33 : 0111010000000000; % sub R5,R0
34 : 0101010010000000; % add R5,R1
35 : 0000001010000000; % mv R0,R5 K <- -K
36 : 0011010000000000; % Skip mvi R5,#Beta+1
37 : 0000000001100111;
38 : 0011000000000000; % mvi R4,#Cont
39 : 0000000001000011;
3A : 0111011100000000; % sub R5,R6 Q == Beta+1?
3B : 1101111000000000; % mvnz R7,R4 No
3C : 0111100010000000; % sub R6,R1
3D : 0111100010000000; % sub R6,R1 Q <- Beta-1
3E : 0011010000000000; % mvi R5,#1111111111111111
3F : 1111111111111111;
40 : 0111010000000000; % sub R5,R0
41 : 0101010010000000; % add R5,R1
42 : 0000001010000000; % mv R0,R5 K <- -K
43 : 0011010000000000; % Cont mvi R5,#Temp Save reg
44 : 0000000001110000;
45 : 1010001010000000; % st R0,R5
46 : 0010110000000000; % mvi R3,#LED LED reg address
47 : 0001000000000000;
48 : 1010100110000000; % st R2,R3 [LED]
49 : 0100100010000000; % add R2,R1 ++[LED]
4A : 0010110000000000; % mvi R3,#11111111111111 Delay
4B : 0011111111111111;
4C : 0001011110000000; % mv R5,R7 Save address of next
instruction
4D : 0010000000000000; % Outer mvi R0,#SW Read switch valuatio
n
4E : 0011000000000000;
4F : 1001000000000000; % ld R4,R0 Nested delay
50 : 0000001110000000; % mv R0,R7 Save address of next
instruction
51 : 0111000010000000; % Inner sub R4,R1 Decrement R4
52 : 1101110000000000; % mvnz R7,R0 jnz Inner
53 : 0110110010000000; % sub R3,R1 Decrement R3
54 : 1101111010000000; % mvnz R7,R5 jnz Outer
55 : 0011010000000000; % mvi R5,#Temp Restore regs
56 : 0000000001110000;
57 : 1000001010000000; % ld R0,R5
58 : 0011110000000000; % mvi R7,#Loop
59 : 0000000000000111;
60 : 0000000000000000; % Alpha-1
61 : 1111111111111111; % Alpha ' '
62 : 1111111111111111; % ' '
63 : 1111111111111111; % ' '
64 : 1111111111111111; % ' '
65 : 1111111111111111; % ' '
66 : 0000000001000010; % Beta 'd'
67 : 0000000000110000; % Beta+1 'E'
68 : 0000000000010010; % '2'
69 : 1111111111111111; % ' '
6A : 1111111111111111; % ' '
6B : 1111111111111111; % ' '
6C : 1111111111111111; % ' '
6D : 1111111111111111; % ' '
70 : 0000000000000000; % Temp
71 : 0000000000000000; % Temp

I have tried a lot, googled things several times. RAM 1-port, ROM 1-port etc. Looked into In-system memory content editor and didn't understand what exactly I was suppose to do with it. And another thing was the ALTSYNCRAM, but I can't find this option in megawizard plug-in manager>storage>ALTSYNCRAM (apparently it's suppose to be there).

Can someone please help?
I have attached an image of the vector waveform that I am getting (functional, 280ns), you may see that nothing is happening to these registers.

proctesting.png
 

j_andr

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And another thing was the ALTSYNCRAM, but I can't find this option in megawizard plug-in manager>storage>ALTSYNCRAM
plug-in manager -> memory compiler -> ram/rom/etc
at the end of parameters specification there is a possibility to define
mif file as an init memory contents;
you can also easily describe ram/rom with init value directly in RTL code;

open any vhdl file, [or create new vhdl file]
edit -> insert template -> vhdl -> full designs -> rams and roms -> ...
---
J.A
 
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apoorvmintri

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Thanks a lot guys! I figured out where I was going wrong =D works now.
by the way, great tutorial jimmy. I really like tutorials being written by people who face the same problem.
 
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