Simple Problem of Systemverilog

Holzapfel said:

Hallo everyone,

Im very new to sv and I have a quite simple question.

I have 3 module now, lets say there a module_1,module_2 and module_3.
Module_1(input a_1,output a_1);
module_2(input a_2,output a_2);
module_3(input a_3,output a_3);

Now I want to instance module_2 and module_3 in module_1, and conncet output a_2 to input a_3, so I create a signal "signal_transport" in module_1:
module_1(input a_1,output a_1);
module_2 instance_module_2(.input a_2(input a_1),.output a_2(signal_transport));
module_2 instance_module_3(.input a_3(signal_transport),.output a_3(output a_3));

But after I run simulation in modelsim, I get error like "signal_transport is driven via a port connection, is multiply driven". How can I solve thsi probelm?

Thanks a lot for help!

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