Simple help with Xilinx block ram

[hdhzero]

Hi everyone,

A simple question: how is the read operation on xilinx's block ram?
Some inferred code that I read on some websites seems to generate the folowing timing:

option 1:
A0 - A1 - A2
XX - D0 - D1

where A0 is the address 0 and D0 is the respective data associated with A0

But on xilinx sheet's, I see something like

option 2:
A0 - A1 - A2
D0 - D1 - A2

In my project, I do not need to change the address during the clock cycle, only on the rising edge. I hope
that the data from an address come in the same clock cycle, not in the following.

 

[TrickyDicky]

The first option will be the option for a synchronous BRam, the 2nd will be for an async ram (but I dont think you can use a BRAM for this - probably only LUT ram).

 

[hdhzero]

Thanks for your reply. Too bad Xilinx does not have async read in block ram as altera does. My design is a simple address register connected to the address port of bram. The data output of bram is connected to the input of the address register. The idea is to the content of memory at the specified address to be the next address that will be accessed. But now I have no idea on how I am going to do this, because xilinx's bram delivers the content on next cycle.

 

[TrickyDicky]

why not just pipeline it?
async rams in altera are not very fast.

 

[hdhzero]

I've tried to pipeline it, but I think it is impossible. Do you see a way to do it?

This is the design: a counter that sends the address to memory, the memory then sends data and data is used to calculate the next value
of counter.

while (true) {
data = mem[counter];
counter = data; // or counter += data or any other operation that needs data value
}

I do not see how I can pipeline this, since data would only be avaiable in the next loop iteration.

 

[TrickyDicky]

just run the clock at 2x output (of the system) data rate. Then the pipeline works fine.

 

[hdhzero]

Is this the only way? Using 2x clock? I know intel uses this idea, but they have direct access to the transistor level. My design runs
on a board (de2-115) that has a oscilator of 50MHz. If I can double to 100MHz, then I can use 2x in the counter update and 50MHz in
the other parts of the design. But if I use 50MHz in the counter update and 25MHz in the other parts, then 2x is a not viable solution =/

I know some boards (xupv2 - virtex 2, e.g.) can increase clock speed, but is the available in other boards?

 

[TrickyDicky]

Most chips have DCMs and PLLs so a 2x clock should be available.

 

[hdhzero]

Thanks! I'll search for it.