From the photograph, I would be surprised if it DID work!
You absolutely MUST connect a decoupling capacitor across VSS and VDD. The reason is that although CMOS ICs draw very little current when in a fixed logic state, they do draw a 'spike' of current as the logic levels change. It is caused by the internal capacitance of the transistors having to be discharged and recharged as the voltage on them changes to the other level. Even the tiny inductance of the wires to the supply, and deficiencies in the supply itself will cause a drop in voltage by the time it reaches the VSS and VDD pins. The drop will be very short, maybe only nanoseconds long but it can be long enough to upset the internal circuits of the IC. Placing a capacitor very close across VSS and VDD gives it a reserve of power exactly where it is needed and help to preven the dip in voltage.
Brian.