wfg42438
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Clock Down must be high for it to work. I suggest you also tie the 'J' inputs to ground. It is a CMOS device so no inputs should be left floating.
Note that the 7447 and CD4511 are not directly interchangeable although they do the same job.
Brian.
What about the LT, BI/RBO & RBI Pins for the CD4511 ?
LT = Lamp Test. Although LEDs are almost always used, the name 'lamp' has stuck for historical reasons. If you pull LT low it turns all the outputs on to check all the 'lamps' are working. For normal use, it should be high all the time.
RBO and RBI = Ripple Blanking Output and Ripple Blanking Input, on the 7447 they can be used to turn all the segments off. This is useful in cases where the display has more than one digit and they have to be multiplexed. On the 4511 the function (BI) is slightly different, it works as an output enable control, if you drive BI low it turns all the segments off so normally you should tie it high. You can pulse it rapidly to control the brightness using a PWM signal.
LE (on the 4511) is the Latch Enable, it allows you to freeze the segment output pattern when the input signal is still changing. You use it when you share the data inputs in parallel with other 4511 devices to route it to one specific IC. Normally you keep it tied low so the number on the data inputs is immediately shown on the LED but if you lift the pin to logic high, whatever was on the data pins at the time it went from 0 to 1 is frozen on the display.
Brian.
The pins are voltage level sensitive and draw virtually no current so it is up to you whether you connect them directly to VCC or use a resistor. The current that would flow through it is so small that even a much higher value resistor could be used if you wanted one. For low cost, you can just connect to VCC but some people would argue that if you did that you lose the ability to pull the pin low (example = for debugging) without shorting out the supply. The choice is really yours, it makes no difference to operation but you must never leave a CMOS input disconnected, because the current they draw is so tiny that there isn't enough to discharge interference pick up on the pin and they could adopt any logic level.
From your description the two ICs seem to be wired correctly. The reset signal should make the output go to '0' and stay there until reset goes low again. If the count intermittently resets by itself, either there is some interference on the reset signal or the power lines are dipping enough to fool the counters into resetting themselves. You should have a capacitor of 100nF directly across the VCC and GND pins of each IC and they should be fitted as close as possible across the IC pins. Also ensure your supply is able to deliver the LED current which varies according to how many segments are lit. For example, if you pass 10mA per segment the current will vary between nothing if all segments are off to about 80mA when they are all on, that is more than a small battery might be able to manage, especially if you have (you should have!) a regulator in the supply to stabilize the 5V.
Brian.
The borrow and carry pins are outputs, so there will be no problem leaving them disconnected.
One further thought. Its not that difficult to damage these CMOS ICs through electrostatic discharge through careless handling.
If they have been "zapped" they can then either misbehave or fail totally.
Always good to have a few extra spares ready stored in conductive foam.
That sounds like the connection to the 5.45v supply is completely open circuit.I checked the VCC pin with a voltmeter and saw something quite odd. When powering up the DC supply i read approximately 4.52 V even though 5.45V
First thing to confirm is that you are using a 40192 and not a 4192.I have done the following for each counter:
Clock up - input frequecny we want to count
Reset- 28.8 sec clock
Clock down- held high
Preset enable- held high
J pins held to gnd
Now for the 4511
Bi-high
Lamp-high
Le-low
A-Q1
B-Q2
C-Q3
D-Q4
CMOS devices are prone to damage if you reverse the polarity betwen the pins. The voltages must never go below VSS (which would mean negative with respect to ground in your case) or higher then VDD. Possibly by not connecting VDD you have broken that rule because VDD was lower than the signal you were counting and possibly the other 'pulled high' pins. However, in my experience, when a CMOS logic gate is damaged that way it tends to draw a lot of current and that would be noticed on your power supply display. I would guess the current drawn by the counter stage would be less than 0.1mA so it wouldn't normally show on the PSU. The 7-segment decoder would draw considerably more and the amount would be the sum of all lit segment currents.
If the ICs are still good, it has to be a problem with your wiring I'm afraid, the connections all seem to be to the right places. Can you post a photograph of the construction please.
Brian.
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