library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity DestinationDecoder is
Port ( W: in STD_LOGIC;
D_Add: in STD_LOGIC_VECTOR (3 downto 0);
Ld: out STD_LOGIC_VECTOR (15 downto 0));
end DestinationDecoder;
architecture Behavioral of DestinationDecoder is
signal LdBuf: std_logic_vector(15 downto 0):= (others => '0');
begin
LdBuf <= (to_integer(unsigned(D_Add(3 downto 0))) => '1', others => '0');
Ld <= "0000000000000000" when (W = '0') else
LdBuf;
end Behavioral;