[SOLVED] Simple clock division--- VHDL

[uselessmail]

Hi there...

How do I divide the clock frequency by 2 for a simple VHDL code?
For eg. if the code is something like this:

process(clock)
begin
      if rising_edge(clock) then
         b_out <= a_in;
      end if;
end process;

Now if I want the same operation to take place, not at every rising edge of (clock) but at that of (clock/2), how do I modify my code?

Regards,
jack

 

[TrickyDicky]

Basically, you dont want to do that. You want to make clock enables. Creating a clock with logic can lead to and unstable design. If you want to divide the clock use a PLL (altera) or DCM (xilinx). Or generate clock enables at the correct frequency.

 

[uselessmail]

Basically, you dont want to do that. You want to make clock enables. Creating a clock with logic can lead to and unstable design. If you want to divide the clock use a PLL (altera) or DCM (xilinx). Or generate clock enables at the correct frequency.

Actually I am already using a DCM and the (clock) here is actually an output from the DCM. The entire synthesis has a lot of operations which use that clock.
In the code, I need just one operation, in this case, "b_out <= a_in" to happen at half the clock frequency.

 

[gongdori]

As TrickyDicky said, it would be better to control your statement using logic, instead of clock.
you can create a signal which invert itself every clock. Then, use this signal as enable signal in your process statement.

If you have to create a clock with half the frequency, you can use PMCD if your device has it. Again, you need to think about the clock phase and delay between the original clock and /2 clock.

 

[FvM]

It's easy to add a clock enable in the present case, keeping a full synchronous design.

process(clock)
begin
      if rising_edge(clock) then
         ck_en <= NOT ck_en;
         if ck_en = '1' then
           b_out <= a_in;
         end if;
      end if;
end process;

 

[uselessmail]

It's easy to add a clock enable in the present case, keeping a full synchronous design.

process(clock)
begin
      if rising_edge(clock) then
         ck_en <= NOT ck_en;
         if ck_en = '1' then
           b_out <= a_in;
         end if;
      end if;
end process;

Thank you!! Thats exactly what I needed!!!

 

[uselessmail]

Is there a similar technique to say multiply the clock by two? Instead of dividing the clock by half, what if one needs to double it?

 

[TrickyDicky]

No simple method:
1. Use a 2x clock for the system clock and have the enables toggle
2. use a DCM/PLL to multiply the clock by 2