Basically, you dont want to do that. You want to make clock enables. Creating a clock with logic can lead to and unstable design. If you want to divide the clock use a PLL (altera) or DCM (xilinx). Or generate clock enables at the correct frequency.
Basically, you dont want to do that. You want to make clock enables. Creating a clock with logic can lead to and unstable design. If you want to divide the clock use a PLL (altera) or DCM (xilinx). Or generate clock enables at the correct frequency.
Actually I am already using a DCM and the (clock) here is actually an output from the DCM. The entire synthesis has a lot of operations which use that clock.
In the code, I need just one operation, in this case, "b_out <= a_in" to happen at half the clock frequency.
As TrickyDicky said, it would be better to control your statement using logic, instead of clock.
you can create a signal which invert itself every clock. Then, use this signal as enable signal in your process statement.
If you have to create a clock with half the frequency, you can use PMCD if your device has it. Again, you need to think about the clock phase and delay between the original clock and /2 clock.