Hi,
I want to know if it is possible to use Tanner EDA to develop IC devices and then export the mask or the final netlist to Silvaco environment in order to simulate the type out process (Lithography ...).
If this is possible, this will allow us to simulate the hole IC design process.
Yes, both tools -can- be used. The question you need to ask,
is whether your foundry will provide the PDK data and accept
a mask database from those tool sets. That comes down to
cases.
thanks for your helpful response,
In fact i am not planning to produce any chip, its all about simulation as Silvaco can simulate the fabrication process.
I have a doubt, i am planning to design a MIM capacitor based on a High-k dielectric, wich is HfO2. so, how to include this particular material inside Virtuoso or Tanner? that is, the capacitor is constructed of two electrode plates(Al for example) separated by the dielectric.
Is there a materiel library in Virtuoso ?
... i am planning to design a MIM capacitor based on a High-k dielectric, wich is HfO2. so, how to include this particular material inside Virtuoso or Tanner? that is, the capacitor is constructed of two electrode plates (Al for example) separated by the dielectric.
Is there a materiel library in Virtuoso ?
well my problem is that i can't fully understand the hole process design flow.
As i know Cadence and Tanner tools are intended for use in semiconductor designs with fabs PDKs (witch contain the process parameters and constraints).
but in my case, i need a to simulate a heterostructures with non conventional materials.
I can do this simulation using MultiPhysics envirenments like COMSOL and HFSS, witch have a materials library with all proprieties (R, Tt , dielectric cons ...).
i am not sure that i best describe the situation, i really need some explanations.
thanks.