Silk screen label overlapping copper entities

[rajeshmp80]

How to check Silk screen label overlapping on the via,pad or any copper entities automatically?

 

[sivamani]

In layout tolls it is not possible but u can verify in CAM350 or some other Gerber verification tools..

 

[SHABU]

Which tool you are using.In cadence we don't have such option.
In altium designer you could define a rule.
Dont know about other tools but whichever tool it may be ,just give a note in fab layer to remove the silkscreen on PAD,Via etc.

Shabu.

 

[Mattylad]

You can do this by not doing it at the start.

In your component libraries make sure that the silkscreen does not cover any pads or can cover adjacent component pads.

Then when moving component names etc turn off everything except for the pads etc that may be covered (and any 1:1 outline layer) so that you can see where not to put the text.

Eventually "you" will automatically not be putting your silkscreen items onto pads.

However, your board manufacturer will run tools and create a silkscreen scratch layer that removes all silkscreen from pads.

It is basically the same as the solder resist layer oversized by a few thou and is merged to be negative on the silkscreen layer.