I suggest peeling back a layer or two of that other-guy's-onion
to know what the "silicon area" is a proxy, for.
Could be cost, could be reliability, could be irrelevant if all
the products are reliable, reliably applied and in packaged
form (that, then setting achievable density in the assembly).
Knowing the real question will let you answer in ways which
benefit you rather than giving you additional work and study
to do. Or might.
Higher voltage can increase die size @ current / Pdiss, as the
increased drift region raises ohmic access resistance and the
FET must then be wider for same conduction loss. But there
is a lot of technology detail in that space, device construction
and cheapskate engineering vs performance vs cost / price
trades. Of course at >1kV you don't have so many options and
that can't help cost or, for that matter, reliability (low volume
affects that, as would pushing into an application niche you
lack the "training lumps" to navigate).