Silicone Area

[kappa_am]

Hi,
I need to compare silicone area needed for conventional 2-level inverter and a 3-level inverter. My first question is how can I make 1200V silicone die comparable to 600V type regarding to silicone area comparison? factor of 2 (even though I think this approach is wrong)?
My second question is how can I calculate silicone area with having switching and conduction losses without having silicone-area-dependent loss factors?

Thank you in advance for your time and comments.

 

[dick_freebird]

I expect that the silicon difference has nothing much to
do with voltage, more just the "3 level" control & drive.
There is not much integrated silicon for 1200V out there.
700V foundries are not that many either. Putting the
voltage problem onto an isolated driver would make your
control chip quite small but cost you what, maybe 6 of
somebody else's piece-part? Disaggregating the drivers
from the control IC could pay benefits in thermal, EMI,
local-bounce issues by optimizing fancy analog and
harsh power separately, with the iso-driver giving that
freedom. Nothing like "not having every HL output
transition pumping your substrate", for bug repellent....

Twice the voltage and 50% more complexity in one bite
seems like a good reason to have a resume ready. Look
at architecture options that might improve the odds.

 

[kappa_am]

Thanks for the comments. In my opinion multilevel inverter would have less chip area because the switching losses are smaller (and often conduction loss too), and main factor for chip area is the losses and heat.
Blocking voltage is more about drift region thickness, I was wondering how I can make it comparable to area!? Or at least is any specific relation between costs?
For the person I am dealing with none of control other merits, etc are important. They insisting on "silicone area calculation".
Any thoughts?

 

[dick_freebird]

I suggest peeling back a layer or two of that other-guy's-onion
to know what the "silicon area" is a proxy, for.

Could be cost, could be reliability, could be irrelevant if all
the products are reliable, reliably applied and in packaged
form (that, then setting achievable density in the assembly).

Knowing the real question will let you answer in ways which
benefit you rather than giving you additional work and study
to do. Or might.

Higher voltage can increase die size @ current / Pdiss, as the
increased drift region raises ohmic access resistance and the
FET must then be wider for same conduction loss. But there
is a lot of technology detail in that space, device construction
and cheapskate engineering vs performance vs cost / price
trades. Of course at >1kV you don't have so many options and
that can't help cost or, for that matter, reliability (low volume
affects that, as would pushing into an application niche you
lack the "training lumps" to navigate).