Signed multiplier in Verilog

[pbernardi]

Hello All,

I would like to make a signed multiplied on Verilog, using an Spartan-6.

Spartan-6 has the DSP48A1 multiplier, that is able to make a pre-sum, and a post-sum. Meaning I can write the following code:

wire [15:0] A, B, C, D;

wire [31:0] MUL = ((A + B) * C) + D;

And the ISE will synthesize a DSP48A1 multiplier.

According the UG389, however, they say that the pre and post operator can be positive or negative; however, I cannot think a way to describe it. What I want is, with two more wires (S1 and S2), make the following:

wire [15:0] A, B, C, D;
wire S1, S2;

wire [31:0] MUL = ((A +- B) * C) +- D;

where S1 and S2 will indicate if the operators are negative or positive. DSP48A1 support this natively, so no additional hardware should be synthesized.

Any ideas?

 

[FvM]

Did you ever consider using the the Verilog signed type?

 

[pbernardi]

Yes, but how would I change the signal on each operation?

for example, if I do:

wire [15:0] A, C;
wire signed [15:0] B, D;

wire [31:0] MUL = ((A + B) * C) + D;

B or D can be signed, but I cannot make a true subtraction; I can only set B or D negative. There is a difference, because my application is clocked and I would like to make the operation in a single clock. If I have to negate B or D and then multiply, I lose one clock pulse.

 

[FvM]

You mean, you want to model the specific DSP48 functionality in Verilog (because you need it in your application for some reason).

I see two options:
- ISE does recognize an additional signed +/-1 factor as description of the respective function
- you need to instantiate a low level DSP48 primitive

 

[pbernardi]

Yes, exactly. Tell me more about first option, please.

you mean, if I define:

wire signed S1;

ISE understand this as a +/-1 signal?

 

[FvM]

The smallest +/- 1 factor is a two bit signed variable. More easily, a mux could represent the sign switching.

I'm not using Xilinx tools so I can't check the suggestions. I also have no feeling about ISE's intelligency in infering hardware from HDL.

Every inference rule has to be implemented by compiler developers explicitely. It can be primarly expected for portable HDL constructs, less likely for vendor specific features like the discussed DSP OPMODE input.