Signed Multiplication VHDL, or real

[DRO]

HELLO,
I am currently designing a filter on an FPGA. I have two major problems.
there is the principal line which implements the filtering (almost like this).
Y(i) <= c*Y(i-1) + b*X(i)
Y(i) is an array of signed(40 downto 0),and X(i) is an array of signed(7 downto 0).X(i) comes from an ADC of 8 bits. Since the "real" value that corresponds to c is a very minute number (0.0000000xx), i need to write it on a 32 bits vector , at least.
The problem is that,if you look very well, i am putting a 32+40 bits vector(c* Y(i-1)) in a 40 bits vector (Y(i)).
I tried to use "resize" function but am not pretty sure that i can get out with it without any damage.
So here is the first problem:
How can i do this algorithm in order to keep the right value needed for Y(i) and at the same time
put a vector that matches Y(i) in it.

The second problem is that i need to transfert the data of Y(i) by UART. so i need to shorten them to 8 bit or somethig. I don't really know how to do that without damaging my datas. I've tried resize again, but it doesn't suit well.

Please, if anyone can help me on this. Thank you.
:-(

 

[axcdd]

You do it in wrong way. DSP units in FPGA are in major 18x18 bit multipliers.

ince the "real" value that corresponds to c is a very minute number (0.0000000xx), i need to write it on a 32 bits vector

It's easier to transform c into fixed numer by multipling coefficients by 2^x and then divide the output by same number.
As for uart cant you send single data by two transfers High value and then low ?.

 

[FvM]

You are apparently implementing a first order IIR low-pass filter.

For a low pass with unity gain, coefficients b and c sum to 1. I don't see how a meaningful low-pass implementation would have very small c values, resulting in b near to 1, or in other words about no filter effect. In contrast, a filter with large fc/fs ratio will have small b values. Intended fc resolution will effectively set the coefficient width and indirectly also the accumulator size.

 

[DRO]

You do it in wrong way. DSP units in FPGA are in major 18x18 bit multipliers.

ince the "real" value that corresponds to c is a very minute number (0.0000000xx), i need to write it on a 32 bits vector

It's easier to transform c into fixed numer by multipling coefficients by 2^x and then divide the output by same number.
As for uart cant you send single data by two transfers High value and then low ?.

Ah got it, you're right!..By the way do you mean that if, for example i have a 16bits length data, i transfert it in two UART frames then deal with them on the receiver?if so, I think i probably can do that, but it would be easier if can just send a single data on a single frame.

 

[DRO]

yes FvM,
I finally figured out. I first changed my coefficieny in order to have them bigger and then uses less larg vectors. I can do it because in my case The fc resolution is not "really" constrained.