The process is entered when the signals in the sensitivity list change. Only if A/B and C/D have inputs that change at the same time will both proc0 and proc1 run in parallel.
If the inputs for A/B change and C/D stay the same then proc0 will be entered and if the result of proc0's AND gate is inverted from the output of proc1 then you'll end up with an X in simulation and a problem with synthesis as you've shorted two outputs together. If the two procs drive their outputs to the same value then the result will be 0 or 1.
If such a thing was done on a physical PCB you would end up burning up one or both parts (AND gate, OR gate) output driver. As VHDL is trying to simulate what can be done in hardware, this is not allowed an will result in X's in simulation and probably an error in most synthesis tools.
You definitely need to keep in mind VHDL is meant to describe hardware.