architecture myarch of big_design_tb is
component detector port( ..., clk: in std_logic; rst: in std_logic; we: out std_logic);
end component;
component writer port( ..., clk: in std_logic; oe: in std_logic );
end component;
signal r: std_logic := '1';
signal clk: std_logic := '0';
signal we: std_logic;
begin
u2: detector port map( ..., clk, r, we );
u3: writer port map( ..., clk, we );
process( clk )
begin
clk <= not clk after 2 ns;
end process;
process
begin
r <= '0';
a <= 4; -- some inputs
wait for 4 ns;
...
end process;
end
port( ..., rst: in std_logic; we: out std_logic);
...
...
process( rst )
begin
if rst = '1' then
we <= '0';
end if;
end process;
process( clk ) -- clk is in the port list
begin
if (clk'event and clk = '1') then
q <= mout; -- these are OK!
if count = 1 then
we <= '1'; -- this is where 'we' is activated
end if;
end if;
end process;
port( ..., oe: in std_logic );
...
...
process( clk )
begin
if (clk'event and clk = '1' and oe = '1') then
if (count < n) then
z <= a(0); -- sending the detected value to the output which is OK
end if;
end if;
end process;
The 'r' signal is the reset and 'clk' is the clock.We e.g. can't see if and how reset or clk of the detector are stimulated
Student edition doesn't support that feature!I presume activehdl has a "trace 'X' source" feature like other industry standard simulators
if count = 1 then
we <= '1'; -- this is where 'we' is activated
end if;
The signal r: std_logic := '1'; in the testbench is the reset signal connected to the rst port of the components.First observation, there's no reset pulse at all.
Respectively, we has initial state of 'U' (uninitialized) instead of '0'
Well yes it has multiple sources if you look at the detector code. It is driven by explicit '0' and '1' in two processes.we should be still set to '1' at 6 ns, thus it either has multiple drivers
process
begin
r <= '1';
wait for 4 ns;
r <= '0';
wait;
end process;
Is that a simulation model? Is it possible to set 1 at time 0?1. While r (reset) is initialised to '1', it is set to '0' at time 0ns. In VHDL, all processes are started at time 0, so r gets set to '0' immediatly.
process( rst )
process( clk )
procss( clk, rst )
Well I have uploaded the codes in previous posts. You can check and simulate it.
I have found that if I use one process (instead of two), then it will be fine. I mean, instead of
Code:process( rst ) process( clk )
I wrote
Code:procss( clk, rst )
Have no idea what is the difference between these two since my code uses std_logic which is the resolved version.
I noticed this back in post #1, I was waiting patiently for someone else to point it out.Code:process( rst ) process( clk )
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