Signal declaration based on a generic + VHDL

dpaul · Jul 26, 2017

Hi,

I have a generic of type standard logic passed down from top-level to module level.

Based on a '1' value of that generic, I want declare a certain set of signals. If the generic value is '0', I want to declared another set of signals.

I think I cannot use generate.
What is the best way to do it?

IDE - Vivado 2017.2

Regards.

---------------------------------------------------------------

Update> Thinking about an alternative like....is it the best approach?

Code:

entity my_entity is
    generic(
        GENERIC_VAL : std_logic := '0'
    );
    port ( 
    .
    .
    );
end my_entity;

architecture my_entity_arc of my_entity is

signal a : std_logic; -- 
signal b : std_logic; --
signal c : std_logic; -- common signal 

begin
    .
    .
    use_gen : if GENERIC_VAL='0' generate
        c <= a;
    else generate
        c <= b;
    end generate use_gen;    
    .
    . 
end my_entity_arc;

TrickyDicky · Jul 26, 2017

Signals cannot be declared conditionally, only assigned to different things. So your attempted approach may be the only option.

You can declare signals locally inside a generate, if that helps, though they are not visible outside of the generate:

Code:

my_gen : if something generate
  signal local_generate_signal : std_logic;
begin
  
  c <= local_generate_signal;
end generate my_gen;

dpaul · Jul 26, 2017

You can declare signals locally inside a generate, if that helps, though they are not visible outside of the generate.

Thanks, never used this, was new to me.

I will implement the approach in #1.

Signal declaration based on a generic + VHDL

dpaul

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TrickyDicky

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dpaul

dpaul

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Signal declaration based on a generic + VHDL

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