It is.
But for different DC input, DSM has different performance. Many theories try to explain this.
That is why dither is so important in Delta sigma pll
and time domain modeling is necessary.
for a 1st order DSM, the best location to add dither is the node before the comparator(1 bit ADC), but sometimes we use accumulator to implement a DSM. It is called 'compact 1st order DSM'. for this structure, there is no such a node. We may add dither to the input or output. It is also effective, but
there is performance loss, because the added dither,in fact also noise, can't be shaped which means more in_bandwidth phase noise of pll.