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Sigma Delta ADC Simulation

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Shady Ahmed

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I am designing a 3rd order Sigma Delta ADC, with 1.5 bit comparator, i modeled the system using ideal components and the system worked as expected.

Now, i inserted the comparator i designed (CMOS Comparator), while simulating , i got confusing results
When i simulate and calculate the FFT (or DFT) using 4096 points, the output is as follows yielding SNR = 74.3 dB
SNR _Post2.PNG


While when i simulate using 8192 FFT points, the output is as follows yielding SNR = 58 dB !!!!
SNR _Post.PNG

How is that possible, has the 8192 points simulation encountered an error (specially that i think there is a memory problem occurs while simulation) ? Can I trust the 4096 points simulation ? specially that it yields a logical value (as expected from the system i am designing)



--- UPDATE

What is more confusing is that i ran the simulation again with the same conditions and everything DIRECTLY after the previous simulation, and it gave the following result !! SNR = 28 dB !! What does that mean ?! i ran the simulation 2 times with the same conditions and different results , does that mean that the first explanation is correct (that the 8192 simulation is erroneous ) ?
SNR _Post3.PNG
Thanks in advance
 
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kemiyun

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Which windowing function are you using? Also can you double check if your coherent sampling is correct.
 

Shady Ahmed

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I am using Hanning Window ..
Sorry but i don't know what you mean by "if your coherent sampling is correct" , could u elaborate more
 

kemiyun

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Okay, here's the deal:

1) Learn about coherent sampling. You should use sampling frequencies and input frequencies that are coherent. Meaning that the input frequency should always be exactly on a bin that is computed by FFT to get the most accurate performance measurement. There's more to it but this is an intuitive explanation. If you get this part wrong you might get worse FFT results, windowing improves this situation.

2) Just a note: always use a window while simulating delta sigma ADCs. But you're doing this anyway.

3) How extensively did you simulate your comparator? Maybe it's not really working in your system. For example if everything else is ideal, does the input signal go below 0? Ideal integrator can handle those stuff but not your comparator.

I couldn't make up anything just from the fft plots, I'm sorry, I don't have any other advice with given information. But the last one you give definitely has a lot of spectral leakage, it shouldn't have that and makes me think that your input frequency is weird or accuracy is too low.
 

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Shady Ahmed

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Okay, here's the deal:

1) Learn about coherent sampling.
Yes i do know that, i just didn't know the exact term of "coherent sampling" , please keep in mind that i mentioned that the system is behaving perfectly as expected when i simulate using 4096 points. I mean that i am doing it right from the DFT point of view & input frequency. However when i use 8192 points (and of course change the input frequency accordingly) I get these strange results.


Bottom Line is (keeping in mind the system design "ideally" should give 75 db):

* the system (ALL IDEAL ) using 4096 --> SNR = 72.4 db
* the system (ALL IDEAL ) using 8192--> SNR = 70.9 db

* the system (ALL IDEAL except for the com ) using 4096 --> SNR = 72.4 db
(it improved, maybe i have a minor error in the ideal comparator)
* the system (ALL IDEAL except for the com ) using 8192 --> SNR is variable !!!!!!!!! yes i mean it, running the simulation several times with ALL the conditions are the same changes the results (the last 2 in the original post is an example) & right now i ran it again , and i got this DIFFERENT result !! SNR = 40.4 (and i got a warning that the system is running out of memory while simulating, but it continued anyway !)

SNR _Post4.PNG


So, my question is ,, is that normal?! Could that be from that memory warning ? Should i trust the 4096 reading and go on with my design ??

Thanks for you help ..
 

kemiyun

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I would say that it's really hard to get better results from an FFT plot. So I assume that your circuit is probably working. But I'd also make sure that it's working with any number of points in FFT, and parametrize things.

Memory warning is probably unrelated, if your input frequency is the same, to get 8192 points you'd need to run it longer so it's probably nothing. But reduce the number of nodes you save.

Increasing reltol may or may not make a difference. I'd also try that, or strobe the FFT points.

One more thing that might be happening is that the ADC is not "settled" when you start feeding in signal and measuring it. What I mean is do you give some amount of time before you take FFT points? Otherwise a few points at the beginning might be slightly wrong and that might cause issues.

I'm sorry that's all I can think of with FFT plots.

Edit: Wait, memory warning might be related actually. If something is unstable, simulator would start using smaller timesteps. In this case it may cause the warnings you're getting.
 

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