shrink the usage of Multiplier and Adder

[nemolee]

Dear all,

I have one complex arithmetic need to implement by digital logic. Is there any good mothed to shrink the usage of Multipliers and adders. Right now in my design, I already use 11 multipliers of 5x5 and 11 adders of 11bit. I need your advice to optimize my circuit area.
Thanks for your full help.

BR

 

[farhada]

The best way to do it to resource sharing. You can create a small memory area, and have a controller that uses only one multiplier and one adder for all the operations and stores the data into different areas of the memoery. It is much much slower but it will save you a lot of resources.

BR,
/Farhad

 

[nemolee]

Thanks for your helpful advice. Right now in our design, I need to process the input data on real time. Do you have another good ideal to do this? Thanks.

 

[feel_on_on]

With CSD u can reduce the use of multiplier and adder!

 

[farhada]

Thanks for your helpful advice. Right now in our design, I need to process the input data on real time. Do you have another good ideal to do this? Thanks.

Hi,
It all depends on what you mean by realtime. If your processing data needs a data flow of 100MHz, you may look into the posibility of using a 200MHz clock and save a few resources by re-using them. It would be greate if you could increase the closk speed to say 4-5 times that will give you a lot more free hand to do what you need to do.

It all depends on if you have FPGA or and ASIC as your target, for ASIC, it will be very difficult to justify the doubling of the clock but for FPGAs sometime it would be an easy change of the design to make it smaller.

If you give more information about your design, I maybe give you a hand.

Bestregards,
/Farhad

 

[nemolee]

If your formula is like this:

R' = R0*4 + {[(R1*X + R2*Y)/2 + R3*Z/2]/2 + {[Round(X*Y/32)*R4 + [Round(X*Z/32)*R5]/2 + [Round(Y*Z/32)*R6 + Round(X*Y/32)*Round(X*R7/32)]/2}/2}/2

The R0~R7 are 6bit data and X,Y,Z are 5bit data. These data are continue to input for 2048 cycle. You have to calculate the result on real time. farhada san, do you have any good method to shrink the gate count.

Thanks for you full help.
BR,

MR.

 

[farhada]

nemolee san,
I am not good with mathematical implementations, but if you send me your VHDL code for this section of the your algorithem, I can give you some feedback. Also, give me some information about the type of device you are targetting, the clock speed, and any other constrains you have. You can send it to my home e-mail at ny_farhad@yahoo.com

Best regards,
/Farhad