Should the phase change of this CE amplifier be 180 degrees?

At DC it is a straight inversion (180) but at any frequency
the Miller capacitance bends the phase, summing a portion
of the input signal (phase=0) into the output through Cds
onto the output node impedance. More, as f increases, as
you see. Cds/(R1 || C1 || (Cblock+Zdriven))

what if I was trying to design a ring oscillator and you had 3 transistor, each output would need a 60 degree phase shift to become 180 in order to feed back to the input to create an oscillator. my minimum phase shift for this transistor is a no less than 87 degrees or so as shown on the graph. If you look up: Design and Simulation of RF CMOS Oscillators in Advanced Design System (ADS) on google search and pick the first link it shows the same transistor that im using and im trying to get a 60 degree phase shift using A = Vout/Vin, but nothing shows less than around 87 degrees on the chart, I feel something is wrong with what im trying to get at with the 60 degrees phase shift and the chart. Please can you explain? Thanks

skatefast08 said:

what if I was trying to design a ring oscillator and you had 3 transistor, each output would need a 60 degree phase shift to become 180 in order to feed back to the input to create an oscillator. my minimum phase shift for this transistor is a no less than 87 degrees or so as shown on the graph. If you look up: Design and Simulation of RF CMOS Oscillators in Advanced Design System (ADS) on google search and pick the first link it shows the same transistor that im using and im trying to get a 60 degree phase shift using A = Vout/Vin, but nothing shows less than around 87 degrees on the chart, I feel something is wrong with what im trying to get at with the 60 degrees phase shift and the chart. Please can you explain? Thanks

Click to expand...

Actually its the 2nd link

Besides the odd-number-inversions you also need gain @ freq
and a phase shift. Three stages is often too short of loop gain @
freq and will "get stuck" at DC threshold or at least fail to make
full swing.

Might want to look at the FET's ft/fmax vs load / bias-point, make
sure the BJT is indeed happy as lashed-up, and then move to an actual
RO (w/ kicker for convenience) to observe as you "tune".

I generally do "digital" ROs looking for full supply swing. A low power
small signal RO would want to operate differently, probably low enough
swing to maintain spectral purity (no distortion). If a VCO, do not neglect
the contribution of the tuning element to the necessary phase-lag (at
resulting lower fOsc).

The phase-vs-freq chart is showing you the bare device (more or less)
and this may well fail as you are seeing. You always have to back off
from device-gain to get oscillation in a loop. So a bare-device plot may
need some thinking, if it's useful at all.

Might repeat your analyses with a series of shunt burden caps (if you
are not trying to get the ultimate technology-limited frequency, but
more of a VCO).