short delay using SRL & long delay using BRAM

[icd]

Hi,

Any idea about how to write the code in vhdl to infer a delay using SRL (Shift Register LUT) or using BRAM. I was told that for a short delay it is better to use SRL and for a long delay it is better to use BRAM !
Also how to calculate the width of the register for a specific delay (say 32 or 64 cycles) ? Is it right in case we need 64 cycles that means 6_bit shift register ?

Thanks

 

[Maxwell077]

Circuits, codes or modules whatever you named in VHDL is clock based(sequential type codes) so any time specifications should be based on clock.
32 cycles means counting 32 rising or falling edges of clock.

I don't understand it well but you want to give an output with a delay value such as 32 cycles. I mean you produced an value and outputted it after 32 cycles.
You can use 5 bits counter.
SRL or BRAM is used for element storage, I have never heard about short delay or long delay. For eg, you can write down VHDL code that infer BRAM and push data into BRAM. If you select first or last data as your output, according to length of BRAM it is delayed.

Good luck