If you have only a iL perturbation, I definitely can see that duty cycle would be shortened. You'd shift Ri*iL upwards which intersects Vea earlier in tripping CMP comparator.The circuit is designed such that the current limit signal can override the EA signal and shorten the duty-cycle to limit the current, independent of the EA signal.
So you are saying that it only limits iL from rising further per cycle but isn't meant to limit the load current in the long run?Hi,
R_sense is not uset to limit the output (load) current.
It is a part of the cycle-by-cycle regulation loop:
According output_voltage_error it charges the coil for a dedicated current to push a dedicated amount of energy to the ouput capacitor.
Klaus
In case of shorted Vo, IL will increase continuously for any D > 0. IL is however clamped by Ea finite output voltage range.
Sure.Do you mean that IL keeps increasing each cycle but then stops when you get to Vdd/(ai*R sense)?
the top circuit / block diagram is not very well drawn. A practical circuit would show a limit on the Vea level - such that this then forms a hard current limit for the power system ....
Yesbut isn't meant to limit the load current in the long run?
My expectation is that flip-flop R input has priority, thus if IL exceeds the limit calculated above, the output stage won't be turned on. In so far, the circuit limits IL absolutely.So the peak current mode only limits the IL rise each cycle but doesn't limit the IL to rise indefinitely in the long run.
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