But, in this case, how does the circuit know when to shift the data?
for the case that a clock exist, data is shifted in every clock cycle.
But, for this case, since there is no clock, how to determine if the data have been shifted in and how to assert that the data shifted in is correct?
First of all, thank you very much for the reply.
So does that mean that the actual circuit that would be synthesized is actually multiplexer and gates?
i.e. for A <= A << 1, we expect a flip-flops when clocking is available. Now that the circuit is in parallel, does it means that it is a selector?