[SOLVED] Shift register implementation and use of its value

ads-ee said:

The way you wrote the shift register code won't work unless there is other code which you neglected to show that takes shift_reg and feeds it back into the input_data. Unless you show everything to do with the code all the way back to inputs and outputs of the module, we can only comment on the code you provide with your question.

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parameter input_width = 8;
parameter bit_width = 1; //in this case to shift 1 bit at a time

input [input_width-1:0] input_data;
reg    [input_width-1:0] shift_reg;

always @(posedge CLK or negedge RST)
begin 
if (!RST) shift_reg <= input_data;
else       shift_reg <= {bit_width{1'b0}}, shift_reg[input_width-1:bit_width]};
end

rogger201 said:

Why?
I tried doing this

Code:

always@(posedge clock) begin 
if (reset) shift_reg = input_data;
else        [COLOR="#FF0000"]shift_reg = {1'b0, input_data[7:1]};[/COLOR]

So all of the data gets loaded in in the first cycle after reset .
This way its achieved in one cycle. Either way I want to use the last bit so I just keep shifting in 0's every clock. Am I going wrong somewhere?

Click to expand...

rogger201 said:

parameter input_width = 8;
parameter bit_width = 1; //in this case to shift 1 bit at a time

input [input_width-1:0] input_data;
reg [input_width-1:0] shift_reg;

always @(posedge CLK or negedge RST)
begin
if (!RST) shift_reg <= input_data;
else shift_reg <= {bit_width{1'b0}}, shift_reg[input_width-1:bit_width]};
end

[/CODE]
I am running this code with different input_data values and it works. Even with different widths of "bit_width" it works by shifting. How could that be possible?
This is all the code thats related to this operation.

Click to expand...