input [7:0] input_data;
input [7:0] send_data;
input [1:0] sel;
output reg [8:0] out;
reg [7:0] shift_data;
//shift register
always @(posedge clock) begin
if (reset) shift_data = 0;
else if (load) shift_data = input_data;
else shift_data = {1'b0, shift_data[7:1]};
end
//this is the module that makes use of this shifted data's MSB along with another input.
always@(input_data or send_data or sel)
begin
case (sel)
2'b00: out = {send_data[5:7], shift_data[0]};
.
.
.
//other cases that are irrelevant here
always @(posedge clock) begin
if (reset) shift_data = 0;
else if (load) shift_data = input_data;
else shift_data = {1'b0, shift_data[7:1]};
end
Code Verilog - [expand] 1 2 3 4 // right shift, shift register with no reset always @ (posedge clk) begin shift_reg <= {serial_in_data, shift_reg[7:1]}; // shifts right one bit on every clock end
Code Verilog - [expand] 1 2 3 4 // left shift always @ (posedge clk) begin shift_reg <= {shift_reg[6:0], serial_in_data}; // shifts left one bit on every clock end
Code Verilog - [expand] 1 2 3 4 5 6 7 8 // left shift with async reset always @ (posedge clk, posedge rst) begin if (rst) begin shift_reg <= 0; end else begin shift_reg <= {shift_reg[6:0], serial_in_data}; // shifts left one bit on every clock cycle that is not during a reset end end
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 // left shift with with async reset and load value always @ (posedge clk, posedge rst) begin if (rst) begin shift_reg <= 0; end else if (load) begin shift_reg <= parallel_load_value[7:0]; // loads the entire shift register with a new value has nothing to do with in_data. end else begin shift_reg <= {shift_reg[6:0], serial_in_data}; // shifts left one bit on every clock cycle that is not during a reset or when load is active end end
The shift register runs empty eight clock cycles after reset.I always want to shift the data. The loading is only necessary on reset. Do we still need a load signal?
The shift register runs empty eight clock cycles after reset.
always@(posedge clock) begin
if (reset) shift_reg = input_data;
else shift_reg = {1'b0, input_data[7:1]};
Why?
I tried doing this
Code:always@(posedge clock) begin if (reset) shift_reg = input_data; else shift_reg = {1'b0, input_data[7:1]};
So all of the data gets loaded in in the first cycle after reset .
This way its achieved in one cycle. Either way I want to use the last bit so I just keep shifting in 0's every clock. Am I going wrong somewhere?
It doesn't have to be in the sensitivity list as it could just be a synchronous reset (i.e. LOAD signal)You keep ignoring post #2. PUT RESET IN YOUR SENSITIVITY LIST!!!
Why?
I tried doing this
Code:always@(posedge clock) begin if (reset) shift_reg = input_data; else shift_reg = {1'b0, input_data[7:1]}; [COLOR="#FF0000"][B]// ads-ee: this is not a shift operation it is an assignment of the input data bits with a single bit right shift (i.e. input_data/2).[/B][/COLOR]
So all of the data gets loaded in in the first cycle after reset .
This way its achieved in one cycle. Either way I want to use the last bit so I just keep shifting in 0's every clock. Am I going wrong somewhere?
It doesn't have to be in the sensitivity list as it could just be a synchronous reset (i.e. LOAD signal)
- - - Updated - - -
That is not a shift register you are loading the same data every clock cycle.
Look at my shift register examples in post #6.
Also clarify what you mean by "I want to use the last bit", which bit are you trying to use and if you know which bit this is in the parallel input data why bother doing any shifting?
The way he wrote it, I don't think it was a synchronous reset (full disclosure: I'm not a verilog guy, I could be wrong).
But, yes, he keeps loading the same data every clock.
I need to use each bit of the input_data in an incrementing manner in every clock cycle.
So in 1st clock, I want to make use of input_data[0]
in 2nd clock cycle, I want to use input_data[1] ... and so on.
The code I have written seems to work by taking the next bit in each clock. Does it seem wrong for what I want to implement?
shift_reg = {{bit_width{1'b0}}, input_data[input_width:bit_width]}
There's no way this should work. Although I'm not a verilog guy, even I can see that every clock you are reloading shift_reg with 0,input_data(7:1). If input_data doesn't change, neither will shift_reg. Just look at post #6. ADS did your work for you.
This is NOT shift register code as it written it is purely an assignment with a sliced bit vector. See the code I wrote in #6, where the assignment uses the same signal name on the LHS and the RHS. Do you know what a hardware shift register looks like? The code I provided describes such hardware...i.e. a chain of flip-flops with Q outputs routed into the next FFs D input.Hello,
Thank you so much for your help. I will keep that in mind. I am new to Verilog so this really helped.
Another small issue I am facing is that I want my "Shifter" to be variable width; as in the number of 0's being appended to shift_reg is variable (parameterized) .
Like
Code:shift_reg = {{bit_width{1'b0}}, input_data[input_width:bit_width]}
this works for non-0 values. When I give bit_width as 0, I get this error
Zero multiple concatenation multiplier, treated as zero width by enclosing concatenation.
It works smoothly with non-0 values but has an issue with 0; clearly because of the generalized way in which it is defined. Is there some way to make it parameterized and yet make it work with 0 width as well?
If you know when to reset how is that different than a load signal? Reset usually means everything is set to an initial power on state.It does work because I can see it in my simulation. It just takes the previous appended value and appends more 0's to it. I need to do it this way because I cannot add the 'load' signal. I cant have additional inputs so I just load the data on reset itself.
It does work because I can see it in my simulation. It just takes the previous appended value and appends more 0's to it. I need to do it this way because I cannot add the 'load' signal. I cant have additional inputs so I just load the data on reset itself.
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