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| library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY final_design is
PORT(clk, c : in std_logic;
s: in std_logic_vector ( 3 DOWNTO 0);
A : in std_logic_vector (3 DOWNTO 0);
q : out std_logic_vector (3 DOWNTO 0));
END final_design;
architecture Behavioral of final_design is
component mux is
Port ( A0,A1,A2,A3,S0,S1 : in STD_LOGIC;
IL : out STD_LOGIC);
end component;
component shifter_unit is
PORT(clk, il, ir,sin : in std_logic;
s: in std_logic_vector (1 DOWNTO 0);
i : in std_logic_vector (3 DOWNTO 0);
q : out std_logic_vector (3 DOWNTO 0));
END component;
component clk_div is
Port ( clk : in std_logic;
clk2: out std_logic );
end component;
signal il, ir, clk1 : std_logic;
begin
uo:mux port map (S(1),S(0),A(0),c,'0',A(3),il);
u1:mux port map (S(1),S(0),A(0),c,'0',A(3),ir);
u2:shifter_unit port map (clk1,il,ir,S(3 downto 2),A(3 downto 0),q(3 downto 0));
u3:clk_div port map(clk,clk1);
end Behavioral; |