I assume this is Vivado? it does not support the 2008 versions of the IEEE packages. It only has selective support for some parts of VHDL 2008. Hence why they call it 200X (to cover both 2002/2008).
Afaik, Intel Quartus Pro 17 and synplify are the only two tools to have proper 2008 support
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But like I said, you're using sla - this is identical in functionality to sll for signed. So use SLL instead.
What do you expect? you're shifting it by 2 (multiplying by 4) and limiting the bit width to 8 bits, and clearly its overflowing. Shifting left always appends 0 to the right (sra and srl both do this). sra appends the sign bit.