non-synthesizable vhdl
Hi,
>>What is the use of shared variables in VHDL, if they cannot be synthesized?
>>Why would someone write non-synthesizable code?
Generally variables are used or can be used in a particular process.It is dedicated to only that process.But Shared variable are those which can be used in more than one process.However,when one process is using the shared varible other process should not use it.
Non-synthesizable code is written for testing and simulation.Through simulation one can know how the program runs.
I hope I am clear.