Shared Bus Valid Signal - Verilog

[forkconfig]

Hi everyone,

I have a shared bus with multiple slaves and a master.
When writing to the bus, the valid signal is pulled high by the master/client.
However, when it comes time for someone else to put data on the bus, the signal is already high.
This is an issue, since there will be no event if it is already high.

What is the best solution:
1) use logic for valid signal such that: if high, pull low; if low, pull high
2) use a pull down resistor, how can I do this in Verilog?
- Someone told me this isn't standard practice in industry, why not? what's wrong with it? what is used in industry?
3) other...please explain...

Thank you!

 

[TrickyDicky]

usually each slave would have it's own request line. the master then arbitrates as to which slave gets control of the bus.

 

[forkconfig]

Hi TrickyDicky, this isn't an access to bus problem.
Please read bellow.

-----------                          -------------
|             |       valid          |           |
|     M      |<-------------->       |     S     |
|             |                       |          |
------------                      -------------

The valid signal is used to identify when the data on the line is valid, because it uses asynchronous transmission.
Since the line is shared the issue is the following:
The master will pull high to signal valid data to the client.
Now the "valid signal" is still high.
The client will respond, and when the data is ready to transmit back to the master he will pull the "valid signal" high.
Since the signal is already high, no even occurs.

Here are solutions that I have been considering:
1) use logic for valid signal such that: if high, pull low; if low, pull high
2) use a pull down resistor, how can I do this in Verilog?
- Someone told me this isn't standard practice in industry, why not? what's wrong with it? what is used in industry?
3) other...please explain...

 

[FvM]

I think, "shared bus" is a vague description. Should we assume a parallel bus? I don't remember any parallel bus that uses a single, bidirectional handshake signal for read and write.

Can you tell about the prerequisites of your bus design?

 

[mrflibble]

Also, is this bus on chip or does it go off chip? Since you ask about "how do I do pullups in verilog"... The short answer is: you don't. You can do things like wired or but you probably don't want to do that either. So how about a better description of that shared bus?

In general it's like TrickyDicky said, request lines + bus arbiter.