shall we call sub program within the for loop in vhdl !!!

Hi,
I have mentioned my code below ,here i have used the procedure and i have called the procedure inside the for loop, but i m getting error when i complied , shall we call sub program with in the for loop. if notn a shall i use for-generate statement to call; the sub program.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sad_ha is
port(
clk,rst : in std_logic;
data_out : out std_logic_vector(7 downto 0));
end sad_ha;

architecture flow of sad_ha is

type mem is array (0 to 255) of std_logic_vector(7 downto 0);
signal m1,m2,ta,tb : mem;

procedure sad
(signal a,b : in std_logic_vector(7 downto 0);
variable p,g,co : inout std_logic_vector(7 downto 0);
signal ao,bo : out std_logic_vector(7 downto 0))is
begin
--carry propagate
p := ((not a) xor b);
g := (a and b);
co := (g or (p and "00000000"));
--sad
ao <= (a xor co);
bo <= (b xor (not co));
end sad;

begin

process(clk,rst)
variable www : std_logic := '0';
begin
if (rst = '1') then
for i in 0 to 255 loop
m1(i) <= (conv_std_logic_vector(i,8));
m2(i) <= (conv_std_logic_vector((255-i),8));
ta(i) <= "00000000";
tb(i) <= "00000000";
end loop;
elsif rising_edge(clk) then
for l in 0 to 255 loop
sad(m1(l),m2(l),ta(l),tb(l));
end loop;
end if;
end process;
end flow;



regards
kanimozhi.m