sfixed to std_logic_vector conversion in vhdl

Hi all;

I want to convert sfixed number to std_logic_vector in vhdl. I use to_slv function as in the code below:

library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;

entity fix is
port (clk: in bit;
nprev: in sfixed (3 downto -4);
op1: out std_logic_vector(7 downto 0));
end fix;

architecture fix of fix is
signal n1: std_logic_vector(7 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1') then

op1 <= to_slv(nprev,n1);

end if;
end process;
end fix;

But an error said:

Error (10476): VHDL error at fix.vhd(19): type of identifier "nprev" does not agree with its usage as "UNRESOLVED_ufixed" type.

Is it I use the to_slv function in the right way? What my mistake? Need helps..Thank you

Doesn't a simple type case work?
P.S.: fixed package to_slv() doesn't have a length parameter, I think

FvM said:

Doesn't a simple type case work?

Code:

op1 <= std_logic_vector(nprev);

P.S.: fixed package to_slv() doesn't have a length parameter, I think

Click to expand...

Yes, you're right..Thanks for helping