SFDR and SNR degradation in post layout simulation of pipelined ADC

[mmkumar]

Hi,

In pipelined ADC, I face degradation of SFDR and SNR in post layout simulations with the coupled capacitance extraction results. Mainly I see with the switched capacitor layout. It works fine with the decoupled capacitance extraction, but with couple extraction, SNR & SFDR drops by more than 25 dB. Can any one help what could be the reason? Where I should concentrate? In my SNR and SFDR plots, I see the entire noise raises up. How do I interpret it?

thanks in advance.

mmkumar

 

[kemiyun]

Re: pipelined ADC layout

Hi there,

I am also very interested in pipeline ADC's. If you can make any progress please feel free to share.

About your question, 25 dB is not a drop that is caused by layout flaws. I believe there may be a dramatic mistake. As you've said you are having problems in coupled extraction, so as far as I can tell take special care of your metal lines. I'm not sure what kind of capacitor you are using but considering a pipeline ADC linearity may be your first limitation so I guess you are using MIM capacitors. They might have worse coupling capacitances than any other.

This is hardly an answer there are much more concerns about ADC layout but it's all I can think of with my limited layout knowledge. Hope this helps.

 

[mmkumar]

Re: pipelined ADC layout

Hi,

Thank you for the reply. using MOM cap. In fact, this simulation set up, we are using idle cap. With the cap extraction, degradation is even worst. Does small drop in the ref signal to each DAC matters?

thanks

 

[kemiyun]

Re: pipelined ADC layout

Try thinking it like this;

Everything outside Sampling Range / 2^bit number in the end is important. Measure it with an ideal DAC to find out the answer you are looking for. But my guess is something more dramatic.

Another thing has just popped into my mind. I believe you are using coeherent sampling, take your time and recalculate frequencies if you are sampling a sinus wave (With a lower frequency of course) to find out if the layout extraction made your system so slow that it can no longer properly samples your ex-frequency.

 

[mmkumar]

Re: pipelined ADC layout

Dear sir,

Do you mean I reduce signal frequency with reference to sample frequency? I reduced sampling frequency there is no use. Does the coupling capacitance between nets on both sides of sampling and feedback capacitance matters? Yesterday, I found few femto farads of coupling cap between the nets, which may appear as a parallel to sampling and feedback capacitor, which changes the gain. But what I see, varying gain error for every sample, even for same DAC positions. Gain varies between 1.9 to 2.1 instead of 2 in the first stage.

thanks & regards,

mmkumar

 

[kemiyun]

Re: pipelined ADC layout

I meant exactly what you've just said.

If few femtofarads disturb your circuit this much I believe it won't work in real life. So I believe the problem is not caused by that.

Gain error is very improtant. And at the first stage it may cause really large INL, DNL problems. So if your INL DNL results are really bad, this seems to be the cause. But by bad I mean very bad, like you barely have some codes. Otherwise it shouldn't be the first cause of SFDR limitation. If it is, you are doing something wrong and you should decrease your bit resolution expectations. But I still do not believe this is the cause, because why would it becomes devastating after femtofarads of capacitance extraction?

Edit: I've remembered you said the entire plot raises up. This seems like a missing code :-D. I hope it is.

With what I know I do not believe I'll be able to help you better. Frankly I'm not experienced and I do not want to lead you away from the real cause. And without further knowledge about what you are doing I can hardly guess the cause. But anyway please share if you can come up with a solution.

 

[sheepissheep]

please share if you can come up with a solution. i'm so curious about it