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setup/hold time violation after clock-gating

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noco3148

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Hi all,

I'm using Design Compiler for synthesis my verilog code.

When I synthesis my code without clock-gating, there is no timing violation in synthesis report and post-synthesis simulation with VCS.

And then I re-synthesis with -gate_clock option to compile_ultra commands and the synthesis report says no timing violation occurs.

But VCS says there are many setup and hold violation in my synthesis result.

Furthermore, the gate count of my synthesis result is also decreased...

I think I made a mistake in my synthesis, but I don't know how to fix it.

Please help me.
 

rca

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The hold could be fixed only after the clock tree synthesis, which not the gated clock insertion.
Then your post synthesis simulation is not relevant for timing checks.
 

noco3148

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Can I simulate it before CTS?
I want to check the functionality before IC Compiler.
 

rca

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You could simulate after synthesis with clock gated added, but you need to do a "functional" sim.
 

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