Sep 15, 2006 #1 P pd_vlsi Newbie level 6 Joined Sep 11, 2006 Messages 13 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,368 hello, hw would one remove....setup and holdup violations....in an semicustom design...consider using Cadence SoC Encounter... if buffers has to be added, resized...whats the difference betwn the buffers for setup and hold time removal..... what r the other techniques....when the automated Timing optimization....cant fix all violations... thanks
hello, hw would one remove....setup and holdup violations....in an semicustom design...consider using Cadence SoC Encounter... if buffers has to be added, resized...whats the difference betwn the buffers for setup and hold time removal..... what r the other techniques....when the automated Timing optimization....cant fix all violations... thanks
Sep 15, 2006 #2 L laglead Full Member level 5 Joined Feb 21, 2006 Messages 262 Helped 22 Reputation 44 Reaction score 8 Trophy points 1,298 Activity points 2,693 For setup time you need clock buffer to change clock skew. For hold time you need delay buffer to slow the data.
For setup time you need clock buffer to change clock skew. For hold time you need delay buffer to slow the data.
Sep 15, 2006 #3 P pd_vlsi Newbie level 6 Joined Sep 11, 2006 Messages 13 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,368 In encounter flow....though we do setup analysis before Clock synthesizing ....in that case hw we can change skew? if we do ....setup analysis after clock tree....then that can be one of the solution.... correct me if i am wrong..... thanks
In encounter flow....though we do setup analysis before Clock synthesizing ....in that case hw we can change skew? if we do ....setup analysis after clock tree....then that can be one of the solution.... correct me if i am wrong..... thanks
Sep 25, 2006 #4 S sevid Member level 2 Joined May 20, 2006 Messages 53 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,711 hi As laglead had said, you can fix ur setup and hold violators when u are P&Ring ur design. and the conmon method is that you can decrease ur frequency if ur clock requirement is not very high. Regards sevid
hi As laglead had said, you can fix ur setup and hold violators when u are P&Ring ur design. and the conmon method is that you can decrease ur frequency if ur clock requirement is not very high. Regards sevid