setup and hold vioaltion in a design

[alam.tauqueer]

Hi,

If we have a design with setup violation than what we should do to remove those violation from the design.

And in case of hold violation what are the different technique to remove hold violation from the design.

Regards,
Tauqueer

 

[mouzid]

Hi,
Delay insertion is one technique using buffers.

 

[alam.tauqueer]

for both setup and hold time violation??

 

[iwpia50s]

For setup violations you need to reduce the datapath delay, which is what datapath optimization does, or decrease the clock speed. For hold violations , you generally need to delay the clock, which can be done by adding delay in the clock path, or by using useful skew.

 

[carv_13]

I believe there are two different cases of hold time violations. One is known as the max delay problem. This can be corrected by using a longer time period for the clock. Another is the minimum delay problem. For this you need to find the path that has minimum delay and insert delay elements on this path to ensure that the signal arrives at a particular point at the same time as rest of the signals.

-Aravind