deepen talati
Junior Member level 1
- Joined
- Sep 10, 2013
- Messages
- 18
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1
- Activity points
- 133
Will setup and hold time for D_latch and D_FF will be same if they are fabricated via same technology?
In multi-clock design,
In case of FF we wait for next rising/falling edge and check the setup time at that particular instant
While in latch we dosent wait for next cycle and capture the data at the time when active level occurs.
ex. case-1
clocks are diff. but same in shape and same waveform for 2 seperate domain FF whom we want to connect
let clock pulse is of 10ns
so we will check the setup time at 10ns and hold time at 0ns
now in this case 2nd FF is falling edge enable
that time why we are not capturing data at 5ns and doing it at 15ns if no data was present initially?
ex. case-2
same clock pulse=10ns
latch works on low-level
that time data is capturing at 5ns and not at 15ns
why??
please clear my doubt.
In multi-clock design,
In case of FF we wait for next rising/falling edge and check the setup time at that particular instant
While in latch we dosent wait for next cycle and capture the data at the time when active level occurs.
ex. case-1
clocks are diff. but same in shape and same waveform for 2 seperate domain FF whom we want to connect
let clock pulse is of 10ns
so we will check the setup time at 10ns and hold time at 0ns
now in this case 2nd FF is falling edge enable
that time why we are not capturing data at 5ns and doing it at 15ns if no data was present initially?
ex. case-2
same clock pulse=10ns
latch works on low-level
that time data is capturing at 5ns and not at 15ns
why??
please clear my doubt.