These values are not usually calculated, they are obtained by characterizing the flip flop in simulation. Basically, you run a sweep of circuit simulations, in each one you change the amount of delay between D pin change and the CLK pin change and you observe the CLK->Q delay for each case. When the CLK->Q change takes longer than a predetermined amount of time (say 50ps, for a modern process) you proclaim the D-change to CLK-change delay in that sim for setup/hold time. This is a vast oversimplification, but it conveys the idea.