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setup and hold time calculation for a flop

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mahanthesh

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setup & hold time calculations for dff

Hello everyone,

What are the things need to be known to calculate setup and hold time of a Flop?

How to calulate setup and hold time?

Eg; If any one say setup time = 2ns and hold time = 1ns

How they arrive at those values? How actually they calculated those values? with what information they arrived at those values?


Thanks in advance
 

spauls

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you need {T c->q } , {T skew} and {T combo}
for set upand hold calculations.
 

eternal_nan

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These values are not usually calculated, they are obtained by characterizing the flip flop in simulation. Basically, you run a sweep of circuit simulations, in each one you change the amount of delay between D pin change and the CLK pin change and you observe the CLK->Q delay for each case. When the CLK->Q change takes longer than a predetermined amount of time (say 50ps, for a modern process) you proclaim the D-change to CLK-change delay in that sim for setup/hold time. This is a vast oversimplification, but it conveys the idea.
 

Thomson

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mahanthesh said:
Hello everyone,

What are the things need to be known to calculate setup and hold time of a Flop?

How to calulate setup and hold time?

Eg; If any one say setup time = 2ns and hold time = 1ns

How they arrive at those values? How actually they calculated those values? with what information they arrived at those values?


Thanks in advance


Hi,
if you have idea of what the D-flip flop is constructed, then you'll definately have the concept of why setup and holdtime must be existed and their calculations as well.

In fact, these two values are in regard to the internal capacitor's charge or dischage time just like the nmos or cmos's charge or dischage.


Suggestions: you may put the diagram of the DFF on your desk, then you can calculate the setup and holdtime according to the device's manufacturing process and the architecture. Of couse, the architecture must be diagramed using basic instances such as inverters and nands. However if you really cares the process of calculating the tsetup and thold, then the nmos or pmos circuit must be analyzed carefully.

Note: you can refer to some basic digital design book such as digital design perspective.

Good Luck!

Thomson
 

steven852

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You may google some course exercises to get the feel. Also, sometimes you may need t_jitter or timing_uncertainty.

Just my 2 cents.
 

spauls

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You can go through Digital Design by John Rabbay, very good explanation of timing and f/f is given.
 

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