setup and hold analysis issues

[p.sivakumar]

Hi

can any body explain for these questions........

1)if your design have one setup violation then can you send your chip into Market ?if yes or no please justify that ?

2)if your design have one hold violation then can you send your chip into market ?if y or N please justify your answer ?

3)for reduceing hold violations generally we are going to insert Delay Buffers.Can you tell me the What is the Safest position or location to add delay buffers for reducing hold violations between reg to reg ?that is ...at

output of 1st reg or
input of 2nd reg or
at combinational circuit between two regs
Which is best suitable place ?and justify your answer with explanation ?

 

[avimit]

A chip having hold violation cannot work. However for setup violation if the chip is forced to work at a lower freq, it will still work. So if the setup is failing say at very high or very low temperatures, with a very low margin, you may want to send it to the market.

Place a buffer right in the middle of two regs.
Kr,
Aviral Mittal

 

[rogger123]

hi
its not necessary that u insert buffers right in the middle of the logic cone. this can lead to setup failures faning out from the logic to a different register(in most complex designs this is the case). one option is to add the buffers at the D input of the failing registers or if u have multiple failures from a given startpoint then u can add the buffer at the q pin of the start point but u have to look at the the fanout from the driving register.

hth
cheers
rogger

 

[love2read]

Just ask customer to work the chip in normal condition, so it won't violate the setup or hold.

 

[shankarmit]

if we have the hold violation.. sure the chip will not work..
if we have setup violation.. then the chip can work at less frequency than operating frequency..

if u have hold violation then insert delay cells at combinational part.. because hold violation occurs due to min delay between two cells...
u can place the delay cell any where between the two registers.. but most perferable is place the delay cell at combinational block...


Regards
Shankar