setting of fir filter

[miryama]

hi every body
I want to use a fir filter in my design but can't adjust setting of it(sample frequency and clock input), i want use decimation 10,input frequency 100M,sample rate 10M .i want to know how it work
my project is in vhdl.
plz help me

 

[jimwu88]

If you're targeting Xilinx FPGA, take a look at the FIR Compiler in Core Generator.
https://www.xilinx.com/support/docu...tion/fir_compiler/v6_3/ds795_fir_compiler.pdf

hi every body
I want to use a fir filter in my design but can't adjust setting of it(sample frequency and clock input), i want use decimation 10,input frequency 100M,sample rate 10M .i want to know how it work
my project is in vhdl.
plz help me