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Setting default value for signal or port (Quartus-VHDL)?

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toninlg

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I would like to set a default value for a signal or a port in VHDL.
For signal I've seen a post speaking about some solutions:

1) process without activity list and a wait; (wait without until) but Quartus wan't a until after the wait statement.

2) if (now < 1ps). Does it works in hardware or only in simulation? I don't know how to use it in my code, because I already update the signal in a process. So I've got an error if I use it outside of the following process.

Code:
PROCESS (INT)
	
		BEGIN
		
			IF (INT'EVENT AND INT='0') THEN

	scmpr <= data (6 downto 0);
	sens <= data(7);
	
	END IF;
	
END PROCESS;
What could be the solution? Is there a mean to execute a processus or a part of a process only at power-up or reset?

I've seen that Quartus supports initialization at declaration but not for all FPGA.
 

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