set_max_delay for ports inside the design

Below is the Verilog code I am trying to synthesize.

I wish to set some max delay constraints on the adders inside this design.

when I try to use the following command for constraining a path of a 16 bit adder (adder_ks16) in the design:
set_max_delay 4 -from {regAcc[0]} -to {sum16[0]}

the tool gives the error:
Error : Could not interpret SDC command. [SDC-202] [read_sdc]

Here regAcc[0] is one of the inputs to the adder and sum16[0] is output.

However if I set the delay on any of the inp/op ports of the module ks_sa1, the command does not give any error.

What command should be given to constrain the path from regAcc[0] TO sum16[0]?


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`timescale 1ns / 1ps

module ks_sa1(SADmin,X0,X1,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,X13,X14,X15,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9,Y10,Y11,Y12,Y13,Y14,Y15,clock,signal_acc,signal_m,signal_set,reset);

input [7:0] X0,X1,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,X13,X14,X15;
input [7:0] Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9,Y10,Y11,Y12,Y13,Y14,Y15;
input reset;
input clock,signal_acc,signal_m,signal_set;
output reg [15:0] SADmin;

reg [7:0] reg1;
wire [7:0] sum0,sum1;
reg [8:0] reg2;
wire [8:0] sum2;
reg [9:0] reg3,reg4;
wire [9:0] sum3,sum4;
reg [10:0] reg5,reg6,reg7,reg8;
wire [10:0] sum5,sum6,sum7,sum8;
reg [11:0] reg9,reg10,reg11,reg12,reg13,reg14,reg15,reg16;
wire [11:0] sum9,sum10,sum11,sum12,sum13,sum14,sum15;
reg [15:0] regAcc;
wire [15:0] sum16;
wire c_out,c_out1,c_out2,c_out4,c_out8;
wire [15:0] notoutAcc,outAcc;

diff d_1(sum0,X0,Y0);
diff8 d8_1(c_out1,sum1,X1,Y1,reg1);
diff9 d9_1(c_out2,sum2,X2,Y2,reg2);
diff10 d10_1( ,sum3,X3,Y3,reg3);
diff10 d10_2(c_out4,sum4,X4,Y4,reg4);
diff11 d11_1( ,sum5,X5,Y5,reg5);
diff11 d11_2( ,sum6,X6,Y6,reg6);
diff11 d11_3( ,sum7,X7,Y7,reg7);
diff11 d11_4(c_out8,sum8,X8,Y8,reg8);
diff12 d12_1( ,sum9,X9,Y9,reg9);
diff12 d12_2( ,sum10,X10,Y10,reg10);
diff12 d12_3( ,sum11,X11,Y11,reg11);
diff12 d12_4( ,sum12,X12,Y12,reg12);
diff12 d12_5( ,sum13,X13,Y13,reg13);
diff12 d12_6( ,sum14,X14,Y14,reg14);
diff12 d12_7( ,sum15,X15,Y15,reg15);


adder_ks16 ks16_1( ,sum16,{4'b0,reg16},regAcc,1'b0);
not n_gate[15:0] (notoutAcc,outAcc);


or or_gate[15:0](outAcc,regAcc,signal_set);

adder_ks16_1 ks16_2(c_out, ,notoutAcc,SADmin);


always @(posedge clock or posedge reset)
begin
if(reset==1) begin
reg1 <= 8'b0000_0000;
reg2 <= 9'b0000_00000;
reg3 <= 10'b00_0000_0000;
reg4 <= 10'b00_0000_0000;
reg5 <= 11'b000_0000_0000;
reg6 <= 11'b000_0000_0000;
reg7 <= 11'b000_0000_0000;
reg8 <= 11'b000_0000_0000;
reg9 <= 12'b0000_0000_0000;
reg10 <= 12'b0000_0000_0000;
reg11 <= 12'b0000_0000_0000;
reg12 <= 12'b0000_0000_0000;
reg13 <= 12'b0000_0000_0000;
reg14 <= 12'b0000_0000_0000;
reg15 <= 12'b0000_0000_0000;
reg16 <= 12'b0000_0000_0000;
end
else begin
reg1<=sum0;
reg2<={c_out1,sum1};
reg3<={c_out2,sum2};
reg4<=sum3;
reg5<={c_out4,sum4};
reg6<=sum5;
reg7<=sum6;
reg8<=sum7;
reg9<={c_out8,sum8};
reg10<=sum9;
reg11<=sum10;
reg12<=sum11;
reg13<=sum12;
reg14<=sum13;
reg15<=sum14;
reg16<=sum15;
end
end

always @(posedge signal_acc or posedge clock)
begin
if(signal_acc == 1)
regAcc <= 16'b0000_0000_0000_0000;
else
regAcc <= sum16;
end

always @(posedge c_out or posedge signal_m)
begin
if(signal_m == 1)
SADmin <= 16'b1111_1111_1111_1111;
else
// #1 SADmin <= regAcc;
SADmin <= regAcc;
end

endmodule
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if you really want this circuit to work, you need a lot more constraints, especially on the asynchrnous part.

Could you help with the error?

I don't have a crystal ball to guess what tool you are using, but here is the answer. Read carefully.

Those are not the primary port, give the full hierarchical path like [get_pins ks16_1/regAcc[0]] .

You should give the complete path....use get_pins or get_ports