Metastability is only one aspect of setup and hold times. I see a common misunderstanding, that a signal transition during the setup and hold window will generally cause metastability. That's not true. For > 99% of the window, the FF output will settle regularly, but you can't predict the state from specification. For an individual FF, the result is more or less forseeable, the actual sampling time changes with V and T (voltage and temperature) variations and within a smaller window of some 10 ps, it's accidental due to jitter effects. Only a transition in a very short metastable window (far below 1 ps for recent logic devices) will bring the FF into an intermediate state with long settling to a final value, it becomes literally metastable.
Metastability can be a serious problem for design reliability and must be considered. The said >99% of trivial setup and hold violations can nevertheless cause unpredicted behaviour of not well considered designs on it's own, without a single metastable event.