Set up and hold violations in flipflops

[ranger01]

Hi,

Can anyone explain setup and hold time with respect to flipflops?

I am not asking the definitions but I want to know why the data should be stable in the window of setup and hold time window around the transition of clock.

 

[HTA]

Setup and hold time on the data input of a flip-flop is needed to ensure that the flipflop is not going to a metastable state (it does not know in which direction to switch because in data was not long enough available). The clock rise and/or fall time is also related to the this. In the data sheet the setup and hold time is specified in relation to the clock input(as well as rise/fall time). If your input is asynchrony to the clock and the setup and hold time is violated the output is not valid for the metastable time. Two flip-flops in series could be used to solve this synchronization problem (e.g. the first stage is clocked with the rising edge of the clock and the second with the falling edge - the time between must be long enough to wait that a potential metastable time has passed).

Enjoy your design work!

 

[FvM]

Metastability is only one aspect of setup and hold times. I see a common misunderstanding, that a signal transition during the setup and hold window will generally cause metastability. That's not true. For > 99% of the window, the FF output will settle regularly, but you can't predict the state from specification. For an individual FF, the result is more or less forseeable, the actual sampling time changes with V and T (voltage and temperature) variations and within a smaller window of some 10 ps, it's accidental due to jitter effects. Only a transition in a very short metastable window (far below 1 ps for recent logic devices) will bring the FF into an intermediate state with long settling to a final value, it becomes literally metastable.

Metastability can be a serious problem for design reliability and must be considered. The said >99% of trivial setup and hold violations can nevertheless cause unpredicted behaviour of not well considered designs on it's own, without a single metastable event.

 

[ranger01]

HTA and FvM thanks for your valuable informations.

But my question is, what makes the flipflop to give unpredicted results, when set up and hold time are violated? I want a detailed picture on the insight of flipflop.

Given the gate delays of the gates which form the flipflop, can you explain these violations?