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Set std_logic_vector bits in a certain range - VHDL

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anasimtiaz

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Hi,

What is the best way to do the following?

Input : 0 0 0 1 0 0 0 1 0 0
Output: 0 0 0 1 1 1 1 1 0 0

i.e. set bits in a certain range?

I want to use this to form a mask to generate valid inputs in a certain range.

Any ideas?
 

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