Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Set std_logic_vector bits in a certain range - VHDL

Status
Not open for further replies.
A

anasimtiaz

Junior Member level 1
Junior Member level 1
Joined
Oct 21, 2006
Messages
19
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Visit site
Activity points
1,424
Hi,

What is the best way to do the following?

Input : 0 0 0 1 0 0 0 1 0 0
Output: 0 0 0 1 1 1 1 1 0 0

i.e. set bits in a certain range?

I want to use this to form a mask to generate valid inputs in a certain range.

Any ideas?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top