serpentine routing - length missmatch

[Step100]

Hi,

When is it necessary to use serpentine routing to match the length between different traces (e.g. databus and addressbus)?

Is there a common formula to calculate the length missmatch between (e.g. D0 and D7) using serpentine routing?

In my case, the processor is running at 100MHz / rise time and fall time is 2ns and should be connected to an SRAM interface. Maybe it`s too slow to thing about such things, but it would be very helpful to know the basics and the calculations of such things... By the way, I`m not in the position to use any kind of simulation tools.

Perhaps someone know a good application note, pdf or book about these things.

best regards
Step100

 

[Anonymous_Ricky]

hi,
you could generate the total etch length report of the signals and then calculate how much mismatch is there and then correct that.
regards,

Ricky

 

[Step100]

hi,
you could generate the total etch length report of the signals and then calculate how much mismatch is there and then correct that.
regards,

Ricky

The mismatch is 40mm between all traces of the databus / adressbus and NRD NWE, CS signals. But I`m not sure if this is too much mismatch or not...

Is there a common way to calculate the maximum mismatch between all datalines, adresslines...? On what terms is it ok to have a mismatch between D0 and D1 of 30mm???

best regards
Step100

 

[senilicus]

You should look at the datasheet of your components. Normally you wil find the allowed mismatch in there.