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# seried fed rectangular microstrip patch antenna

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#### everjordan

##### Newbie level 4
series fed rectangular microstrip patch antenna

hi guys
I'm designing a series fed microstrip rectangular patch antenna operating at
26Ghz.

The microstrip antenna is consist of 6 patch and feeding line is 50ohms.
Below is the design by using hfss 11.

sidelobelevel is less than -25dB
s11 is less than -20dB

I design one patch antenna by using some equation.

In this case, 26ghz is not resonant frequency. 26GHz<x<27.x
And sidelobe level is around -1x.
So, I move to design frequency from 26GHz to 27GHz.
I used below equation by using matlab.
And the connection length between patch and another patch set the same
length of the patch antenna.
----------------------------------------------------------------
% method to obtain patch's length
clc;
clear all;
h = 0.79;
f =27;
f = f.*(10^(9));
c = 3.*10.^(8);
er = 2.2;
w = 1000*c./2./f.*sqrt(2./(er+1));
ee = ((er+1)./2 ) + ((er-1)./2).*(1+12.*h./w)^(-0.5);

deltal = h.*0.412.*(ee+0.3).*((w./h) + 0.264)./(ee-0.258)./((w./h) + 0.8) ;
l = 0.5.*c./f./sqrt(ee) - 2.*deltal./1000;
l = l*1000;

w
l
--------------------------------------------------------------------------
As a result, S11 is less than -20dB.
However, the radiation pattern is not good...
SLL is around -1xdB.
And the value of first sidelobe is not good.

How to reduce the first sidelobe level?
And then how to reduce both sidelobe level and s11?
I try to reduce length of the connection line but result is not good.
(-0.0x step or +0.0x step)

---------- Post added at 15:31 ---------- Previous post was at 14:56 ----------

I haven't connect the quarterwave transformer.
I used HFSS skill called deembed and just look in front of the feeding line.
Again, I just look patches.
The results not all designs but patches.

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calculate value of Q (quality factor) and use lumped elements for making your antenna resonant.

hi
if the shape of like the pic which u attached it look impossible to vanish the side loop

hi
why can't I reduce side lobe of this pic?

It'd shown that unwanted sideloop is charge , consult the book on Analog Circuit Design .

Thing make sure is elabolated model to simulate circuit for furture design (Q>60)

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