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Serial-to-USB interface design

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ericmar

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Hi,

I had designed a Serial-to-USB interface adapter using the CP2102 from Silicon Laboratories. Below is my Schematic & PCB design. I want me PCB design to have minimum EMI effect. I am not sure about the trace width of my routings though.

Sch1.jpg


In my design, the bottom layer is filled with Signal GND plane and small plane of USB connector shield at right hand side.

USB1.jpg


I read from somewhere that the USB DP/DM traces should maintain nominally 90ohms differential impedance and thus, the DP/DM traces should have trace width of 22mil and 7mil spacing but it just doesnt make sense to me since it will make no clearance in between of the DP/DM traces.

"A continuous ground plane is required directly beneath the DP/DM traces and extending at least 5 times the spacing width to either side of DP/DM lines." What does this mean?

From: hxxp://www.smsc.com/main/anpdf/an1311.pdf

Can anyone kindly take a look and give me some comments.

Thanks,
Eric Mar

Added after 3 hours 21 minutes:

Does this design considered as high speed or low speed if I m going to make it run at a speed lower than the 1.5Mbps?
 

vvvvv

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90 ohm is impedance strongly required
for 480Mbit if length of trace more then 0.5cm
for 12Mbit more then 20cm
for 1.5Mbit more then 160cm

22mil widths and 7 mil spacing means
two traces witdh 22mil each and 7 mil
between EDGEs of traces (not center lines).

Ground plane below DP and DM traces
necessary for signal integrity DP and DM.
When DP, DM both have equal width, equal distance
between each other and have below them gorund plane
= conditions for uniform impedance is performed and
will not signal distortion that passes through DP,DM
Conditions for importance of precense ground plane
under DP,DM the same :
480Mb = 0.5cm
12Mb = 20cm
1.5Mb = 160cm

It's needed only for signals higher 40MHz.
In your case it's not important

Formulas for signal integrity :
impedance discontinuty will influence when
length of traces in inch more then
rise time in ns.
Rise time equal for digital signals 0.1*Tclk.
Example : 12MHz = Tclk = 1/12MHz = 83ns
rise time = 0.1*83 = 8.3ns
That critical trace length is 8.3inch or 8.3*2.5=20cm.
 

ericmar

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Thanks vvvvv!

Is tat mean I dont need to care abt the 90ohms differential impedance at all?

Wats the freq range for low/high speed board design?

Thanks again.
 

vvvvvv

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yes you may not care about 90 ohms
critical frequency for high speed 40MHz
 

    ericmar

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philba

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Interesting discussion. I learned something.

I'm not sure your optoisolator is going to work for RX. Doesn't the phototransistor require a pull-up to +V?
 

ericmar

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philba said:
Interesting discussion. I learned something.

I'm not sure your optoisolator is going to work for RX. Doesn't the phototransistor require a pull-up to +V?
You're absolutely right!

However, it does work for the optoisolator w/o a pull-up resistor. I think main becoz of the optoisolator is able to work at very low power.

I did some changes on the circuit as to make it more stable and would upload the new design later for ur reference.

Let us all learn together!

:)
 

philba

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your Tx should work but I don't see how the transistor on the Rx will generate any voltage by itself - that's not how phototransistors work.
 

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